Making Computers Count

Level vs Edge Sensitive

Level Sensitive

Figure 1. D-Latch Output

Edge Sensitive

Figure 2. Edge vs. Level Sensitivity

Edge detector and D-FlipFlop

Figure 3. Pulse Detector and D-Latch

Behavioral Implementation

module byte_memory_ff(
    input [7:0] data,
    input store,
    output reg [7:0] memory
);

    always @(posedge store)
        memory <= data;

endmodule

State Tables

Excitation, Characteristic, and Truth Tables

Truth Table

Table 1. D Flip Flop Truth Table
Input	Q_current	Q_next
0	0	0
0	1	0
1	0	1
1	1	1

Characteristic Table

Table 2. D Flip Flop Characteristic Table
Input	Q_current	Q_next
0	X	0
1	X	1

Excitation Table

Table 3. D Flip Flop Excitation Table
Q_current	Q_next	Input
0	0	0
1	0	0
0	1	1
1	1	1