Lab 01 - ECE230L Introduction

Welcome to ECE230L! In this lab, we will endeavor to give you a glimpse into the true inner workings of computers. This is the companion lab to the ECE230 lecture, both focusing on digital logic. Generally, you can expect to be using things in this lab that you learned the prior week during lecture. You will be learning the practical application of a wide range of Verilog features as they relate to digital logic design, culminating in a final project that will give you a glimpse into the world of computer architecture to prepare you for ECE330 after this.

Each lab will have several "deliverables" as such listed at the bottom of the document for each assignment. They will typically be one or more Verilog modules you will be expected to implement to achieve some goal. The labs are graded fairly simply – demonstrate the function of the Verilog code on the Basys board to a TA/instructor, ask a few questions, and you get checked off. Partial credit can be awarded as the lab instructor sees fit by examining code committed to each GitHub project if you are unable to complete the assignments during the lab. They are all designed to be completed within the allotted time, however, and you should rarely need to use this. In addition to demonstrating in the lab, there will be lab reports to write about each lab. Details for these, and how they are graded, will be included with each lab.